1. Field of the Invention
The present invention relates to microelectronic circuits and, more particularly, to single-event effect (SEE) resistant or xe2x80x9crad-hardxe2x80x9d circuits.
2. Description of Related Art
Integrated circuits used in space, weapons, or aviation applications must be more resistant to radiation than circuits used in other applications, because they are more likely to be exposed to radiation, and because their reliability is often more critical. Such solid-state circuits are vulnerable to transient disturbance of the output voltage state from particles that pass through transistors or other circuit elements. These disturbances can result in operational failure of the circuit. Some examples of these particles are:
Alpha particles: These are the byproducts of the natural decay of elements.
Energetic (having kinetic energy) protons, neutrons, electrons, and all the natural elements. These are abundant in intergalactic space, earth orbital space and even at high atmospheric altitudes (e.g., commercial flight altitudes) in a wide range of energies.
When a particle passes through a transistor (or any device), hole-electron pairs are created along the track length. The electrons will migrate toward high voltage state nodes of the struck transistor, resulting in a discharging current on that node. If the discharging current exceeds the current drive of the transistor holding the high voltage state on that node, the node will transition to the undesired low state. The holes will migrate toward low voltage state nodes of the struck transistor resulting in a charging current on that node. If the charging current exceeds the current drive of the transistor holding the low voltage state on that node, the node will transition to the undesired high state. The number of hole-electron pairs created by the particle is finite, so the node voltage disturbance is temporary. The result is that a particle can cause a transient disturbance of the output node of a logic gate. The density of these particles is smallxe2x80x94small enough that these disturbances are treated as singular events in time. Thus, a transient disturbance caused by a particle strike is known as a single-event transient (SET).
A circuit node will return to the desired voltage state after a SET. Thus, a SET, in and of itself, is not a problem. What is a problem is the consequence of having a temporary voltage disturbance on a circuit node. If the node is in a clock network, the SET can generate a false clock pulse in a portion of the system. If the node is in a data storage element, the SET can flip the stored bit to the opposite state. If the node is in the logic that feeds the data input to a latch (or flip-flop, register, etc.), there may or may not be a consequence from the SET. If the data input recovers to the valid state from a SET before the latch closes, there is no consequence. However, if the data input does not recover to the valid state from a SET before the latch closes, then the wrong data state is loaded into the latch. When the SET results in the wrong data state in a closed data storage element, it is known as a single-event upset (SEU). More generally, logic errors caused by SETs are known as single-event effects. The susceptibility of modern integrated circuits to single-event effects is heightened by the reduced feature size and higher clock speeds that are otherwise very desirable.
Some solutions attempting to mitigate SEU susceptibility require the use of relatively complex combinational logic circuitry to provide logical or temporal isolation of single-event effects that would otherwise cause errors, but such solutions typically are not area efficient.
Further, logic and temporal isolation circuit solutions can affect overall circuit speed and may, in some cases, be applicable only to storage circuits. Thus, an area-efficient solution that provides a high degree of SEU hardness and that is also applicable to various circuit types (such as combinational logic circuits as well as memory circuits) is needed.
In a first aspect, a radiation hardening circuit is provided, where the circuit includes a first transistor that has a source terminal, a gate terminal, a drain terminal, and a body terminal. The circuit also includes a resistor with a first node and a second node, and the first node of the resistor is conductively coupled to a reference voltage node while the second node of the resistor is conductively coupled to the body terminal of the first transistor
The circuit also includes a second transistor having a source terminal, a gate terminal, a drain terminal, and a body terminal. The drain terminal of the second transistor is conductively coupled to the source terminal of the first transistor and the gate terminal of the second transistor is conductively coupled to the gate terminal of the first transistor, so that a particle strike on either of the two transistors will not result in a single-event transient.
These as well as other aspects of the present invention will become apparent to those of ordinary skill in the art by reading the following detailed description, with appropriate reference to the accompanying drawings.